1. Field of the Invention
This invention relates, in general, to a modulus control loop and, more particularly, to a modulus control loop for controlling a phase locked loop.
2. Description of the Background
In the background art a modulus control loop is coupled from the modulus control output of the counter control logic of a phase locked loop (PLL) to the control input of a dual modulus prescaler. At higher frequencies the time to input a clock signal input the PLL from the prescaler is less than the time required to transmit the control signal back to the prescaler. When this occurs the PLL can completely miss an entire count. This problem is remedied by either reducing the input clock frequency, thru increasing the prescaler divider and corresponding reduction in reference frequency, or by reducing the frequency of the clock signal prior to receipt by the prescaler. Unfortunately, these remedies either add significant complexity to the circuit; reduce the output frequency resolution; or reduce the reference frequency.